Traditional approaches to testing, diagnosing and repairing on-chip memories involve a testing architecture that includes a 16-state state machine and at least four input/output (I/O) pins in the design. The memories are tested using memory built-in-self-test approach (MBIST), which utilizes a number of algorithms to test the memories. To ensure that no defects are present in the design, large number of algorithms are run to test the memories, which results in very long test-time for a chip.
In some instances, memories may be tested in parallel to reduce test time. However, with the abundance of memories present on a current chip, running all of them in parallel causes the chip to consume substantial amounts of power, which may damage or destroy the chip. Moreover, a large number of chip designs have multiple power domains out of which not all the domains are active at the same time. If memories are present in different power domains then a lot of extra isolation and/or retention logic is required to test these memories properly.
Some further approaches involve testing memories in a group in parallel, but in series with another group. This approach attempts to balance the test-time and power, but has a number of limitations. For example, with this approach, all the memories are still associated with a single set of test-data-registers (TDRs) included in the testing architecture. Each TDR in a set of TDRs acts as a scan chain and has an associated instruction. The loading and unloading of these TDRs (based on associated instructions) is performed at the frequency of the test clock input (TCK), which is relatively small, so it takes a long time to load and unload the TDRs. Furthermore, the loading and unloading of these TDRs is done quite frequently to schedule the memories, observe the results, and take appropriate actions, thereby increasing the test-time.
Moreover, if a chip has memories in different power domains then there exists no proper method to test the memories. For example, the memory testing logic may be inserted into the proper power domain, but when the memory testing logic is stitched in one set of TDRs crossing through all the power domains, state retention and isolation logic is required to make that work which is unnecessary overhead in terms of hardware.